Indium EMSNow Durafuse x

iNEMI’s 1st Level Interconnect Void Characterization Project Reports Phase 1 Results

Phase 1 Report: 1st Level Interconnect Void Characterization Project
February 2 & 3, 2021

Flip chip packages are key solutions that help drive high-density and improved interconnect for advanced electronics packaging. However, the formation of small voids (micro voids) can occur in solder-based flip chip joints during the assembly process, and these voids tend to grow after multiple reflows (solid-liquid-solid). The impact of these micro voids on package performance and reliability has not been well characterized to date. For example, micro voids in 1st level interconnect materials can be a concern for applications that involve high electrical and thermal flux. Voids can also have an impact on electromigration in the joint, adversely affecting the reliability of the electrical interconnect. There are presently no guidelines or standards that define an acceptable percentage of voiding or how the percentage of voiding relates to the reliability of the assembly.

Phase 1 of the 1st Level Interconnect Void Characterization project has studied voids in flip chip interconnect to determine their location and volume in an effort to understand how the voiding affects product reliability, and what level of voiding is acceptable while maintaining reliability requirements. This webinar will report on Phase 1 results.


Two sessions are scheduled and are open to members and non-members. Advance registration is required. If you have any questions or need additional information, please contact Masahiro Tsuriya (

Session 1
10:00 a.m. JST (Japan) on Thursday, February 4
8:00 p.m. EST (Americas) on Wednesday, February 3
Register for this session

Session 2
Thursday, February 4, 2021
8:00 a.m. EST (Americas)
2:00 p.m. CST (EMEA)
10:00 p.m. JST (Japan)
Register for this session

x Brown