Call-for-Participation: iNEMI Webinar 1st Level Interconnect Void Characterization Project

Two sessions scheduled December 12, 2019

Flip chip electronic packages are commonly used to address today’s high-density interconnect needs. However, the formation of small voids (micro-voids) can occur in solder-based flip chip joints during the assembly process and these voids tend to grow after multiple reflows. This can be a concern for certain applications that involve high electrical and thermal flux across the flip chip where void formation can have an impact on electromigration in the joint. The presence of a void can accelerate complete open failure due to electromigration.
This project will study voids in flip chip interconnect to determine their location and volume. It will also seek to understand how voiding in 1st level interconnect affects product reliability and what level of voiding is acceptable while maintaining reliability requirements. The project will have two distinct phases:
  • Phase 1: Determine recommended inspection capabilities for micro-voids in 1st level interconnect materials
  • Phase 2: Determine the relationship between voids and the electrical and mechanical reliability of the assembly
The project is expected to develop technical guidelines regarding acceptable voiding characteristics for flip chip interconnects that can be shared with industry and relevant standards bodies.
The 1st Level Interconnect Void Characterization Project is led by Lee Kor Oon (Intel) as project leader, with Sze Pei Lim (Indium) and Kiyoshi Ooi (Shinko) as co-leaders. Click here for additional project information.

Call-for-Participation Webinars

If you are interested in this project, please join us for one of our call-for-participation webinars. These webinars are open to industry (iNEMI membership is not required). Participants must register in advance — click on the links below to register. For additional information, please contact Masahiro Tsuriya (

Session 1 (APAC)

Date: December 12, 2019
Time: 10:00 a.m. JST (Japan)
          9:00 a.m. CST (China)
          8:00 p.m. EST (U.S.) on Dec. 11
          5:00 p.m. PST (U.S.) on Dec. 11
Register for this webinar

Session 2 (Americas and EMEA)

Date: December 12, 2019
Time: 7:00 a.m. EST (U.S.)
         1:00 p.m. CET (Europe)
         8:00 p.m. CST (China)
         9:00 p.m. JST (Japan)
Register for this webinar
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