Bespoke Silicon Rattles Chip Design Ecosystem
Bespoke silicon developers are shaking up relationships, priorities, and methodologies across the semiconductor industry, creating demand for skills that cross traditional boundaries, and driving new business models that leverage these enormous investments.
Bespoke silicon designers today are a rare breed, capable of understanding the unique requirements of a specific domain, as well as a growing array of issues that can crop up in multiple stages of the design flow. At the most basic level, they need to understand what works best in hardware, what works best in software, and how to tightly integrate both to optimize performance and power.
“The software architect or the system architect needs to know what it takes to do silicon,” said Mo Faisal, CEO of Movellus. “Otherwise, they will be tossing out algorithms that are not practical for implementation in actual silicon. Software architects really need to be comfortable with what happens in hardware.”
Software allows bugs to be worked out in the field, and it provides a way to minimize obsolescence. But it also has to be written in a way that doesn’t impact performance. Kam Kittrell, vice president of product management in the Digital & Signoff group at Cadence, noted that Jim Keller — who has a long history of developing chip architectures at companies like Apple, AMD, and Tesla — “told his team that whatever chip they’re making, make sure it is programmable, and that they can write software for it. It seems like something they would know to do, but apparently, it’s not that easy.”
Software is one critical piece. Another one is advanced packaging, which is essential in high-performance chips with some type of AI, because not everything will fit on a single reticle-size chip.
“We have long worked with the traditional chip architect, but now we’re working with the system architects,” said Marc Swinnen, director of product marketing at Ansys. “This is a skill set that goes beyond the single chip. They now have to worry about issues with the PCB, package, thermal, and mechanical. These are all things the chip designer never had to worry about, but now does. You put in two different chips at different temperatures, you get thermal differences, and they warp.”
At the same time, there are organizational challenges that come with this. “The chip was done by one person, the thermal was another. Packaging was over in Israel, the thermal is in Bangalore, and now you need a team that has all these capabilities assembled together. A lot of companies are just not set up to do that. The designer rarely talks to the packaging designer, or it’s way after the fact. With thermal, if you take two chips that are going to be hot in their activity and you put them right next to each other on the interposer, that’s never going to work. It’s dead before we even start the design. If you only figure that out at the packaging stage, it’s too late to do anything, and you can’t ECO your way out of that. Organizationally, people are challenged to solve these problems because they’re not set up to do it.”
The good news is that there is plenty of room for improvement, and chip architects are enjoying an unprecedented level of freedom. The bad news is they have so many options that it is impacting design schedules.
“System engineers can now design their own bespoke silicon because they understand their system problem. They’ve got the real-world datasets. They’ve got the AI. It’s a glorious situation,” said Kevin McDermott, vice president of marketing at Imperas. “But please invite the verification team to the table. I might have another generation, and I’d like an option or a mode here. I’d like to flip this over. I would like to have multiple choices and options all the way through that. The verification person will sit down and tell you to validate and verify the core. But for every option, you’ve doubled the work, because you now need to test with and without. We all love the idea of the freedom and innovation — as long as we have some standards here to tape out on a reasonable timeframe.”
