SMIC Employs Mentor Graphics Calibre PERC for Reliability Verification of Multi-Power Domain SoCs
May 23, 2012
Mentor Graphics Corp. and Semiconductor Manufacturing International Corporation has announced that SMIC is using the Calibre® PERC circuit reliability verification solution as part of its latest electrostatic discharge (ESD) protection design methodology.
SMIC's approach helps ensure whole chip ESD protection for
its customers' large, complex SoCs, including all I/Os, embedded IP blocks from SMIC or third party sources, and eFuse embedded memory. SMIC adopted the Calibre PERC solution because it provides the unique ability to automatically combine schematic (netlist) and physical layout criteria and measurements to perform advanced reliability checks that until now were primarily done manually.
"New applications and use models create more difficult ESD protection challenges for designers due to increasing breakdown voltage variability, and a greater number of vulnerable circuit nodes at the interfaces between voltage domains in low power designs," said Tianshen Tang, Vice President of Design Service at SMIC. "We offer a multi-pronged approach that includes robust ESD protection in our IP libraries, running circuit checks for our customers using Calibre PERC with SMIC rule decks, and consulting services to assist customers with their specific ESD performance and reliability needs. We will also issue Calibre PERC design kits for our customers by mid-year so they can define and run their own checks."
SMIC uses the Calibre PERC platform's Logic-Driven-Layout analysis capability to ensure that all designs, including SMIC IP libraries and customer designs, conform to SMIC's enhanced ESD design rules. Some of the key ESD protection techniques include:
• Integrated ESD protection with a common ESD ground bus for the entire I/O ring to ensure safe discharge
• Cross-voltage domain and analog-digital interface protection
• Fast trigger protection devices for enhanced design margin
• Low leakage protection circuits and high latch-up immunity
• Local ESD protection for IP cores and eFuse memories
The Calibre PERC product not only detects violations, but provides designers with a holistic environment for debugging circuit reliability problems with an integrated view of circuit connectivity, topology, physical layout and design rules that is not available in any other tool.
"Designers are realizing that regardless of the process dimension they are targeting, circuit reliability checking is a growing issue that requires much more sophisticated automation than in the past," said Michael Buehler-Garcia, Senior Director of Marketing for Calibre Design Solutions at Mentor Graphics. "The impact on yield and long-term reliability grows at each successive node, so designers should plan to make advanced reliability checking an integral and permanent addition to their design flows."