UMC validates the Mentor Graphics Calibre xRC
Jun 29, 2004
Parasitic extraction solution for 90nm process technology
Mentor Graphics Corporation (Nasdaq: MENT) announced that Calibre xRC, Mentor's transistor-level parasitic extraction solution, has been silicon validated by UMC for its 90 nanometer process technology.
Calibre xRC is an advanced tool that meets the stringent demands of nanometer technologies. Especially significant for 90nm designs is the pairing of Calibre with Calibre LVS, the layout vs. schematic (LVS) tool. This combination provides actual measured device parameters that can be back-annotated to the source netlist for post layout analysis. This is a key factor in accurate nanometer silicon modeling, positively impacting yield and contributing toward first pass success of integrated circuit (IC) designs.
"At 90nm, it is imperative that our customers have access to the most advanced methods of achieving design and silicon success," said Ken Liou, division director, Design Support Division at UMC. "Calibre's accuracy, capability and integration in physical verification and parasitic extraction will provide a proven solution that our customers can quickly adopt in their flows."
"UMC is ensuring the success of nanometer designs by directly addressing the physical issues that can hamper that success," said Joe Sawicki, vice president of the Design-to-Silicon division at Mentor Graphics. "By validating tools engineered for advanced processes, customers will be prepared for the shrinking geometries of the future."