Applied Materials and Agilent develop benchmarks for testing copper/low k film reliability

Goal is to optimize new equipment for customers' advanced devices Applied Materials, Inc. and Agilent Technologies, Inc. today announced they have developed benchmarks for testing the electrical reliability of new copper and low k materials used in chipmaking. The resulting characterizations of these materials have been shown to optimize and speed the development of equipment and production specifications for manufacturing advanced interconnects. "Applied's collaboration with Agilent is helping us to more rapidly characterize and develop robust copper processes through improved reliability data collection and analysis," said John TC Lee, general manager of Applied Materials' Maydan Technology Center Group. "We expect this work to further enhance our capability to create products that address our customers' most the advanced manufacturing needs." Market research firm Gartner Dataquest estimates that the percentage of silicon manufactured using copper and low k materials will grow from 15 percent this year to 42 percent by 2007. The joint benchmark project was conducted at Applied Materials' Maydan Technology Center facility located in Santa Clara, Calif., using the Agilent Parallel Parametric Reliability (PPR) Test System. Applied Materials uses the Agilent PPR for emerging 90nm and 65nm applications. New materials and processes being implemented at these technology nodes produce unfamiliar phenomenon that traditional reliability tools can neither detect nor efficiently analyze. Agilent's PPR system can be tailored to accurately detect and analyze physical phenomenon and reliability lifetime. "Today's thinner oxides and gate dielectrics are making it almost impossible to package the devices without destroying them," said Minoru Ebihara, vice president and general manager of Agilent's Hachioji Semiconductor Test Division. "As process technologies move into the 90nm range and 300mm fabrication, it is becoming imperative to perform reliability testing on the wafer itself in order to prevent waste of expensive processed wafers. This is where our Parallel Parametric Reliability testing capability adds real value." Until now, the only way to perform long-term reliability testing on wafers was to package the devices, which is both expensive and time consuming. The PPR system directly tests up to 96 four-terminal devices on-wafer and in parallel, and can further perform simultaneous reliability testing of multiple sites on a single silicon wafer, supporting faster characterization of next generation processes and equipment.Source: PCBnewsline