Zuken and Aldec partner to offer complete FPGA design and verification flow
May 24, 2007
Adopting programmable devices is set to become significantly easier as a result of a partnership between Zuken, engineering consulting company, and Aldec , HDL verification specialists.
By combining Zuken's expertise in system- and board-level electronics design and verification with Aldec's mixed HDL verification technology, the two companies will be able to offer a combined design and verification flow for flexible field programmable gate array (FPGA) devices on printed circuit boards (PCBs). At this time, the partnership will focus integration efforts on Zuken's enterprise-wide PCB design suite, CR-5000.
Initial development will allow designers to launch Aldec's mixed language simulation technology from within CR-5000 System Designer for access to project-specific design data.
It will be possible to perform FPGA timing simulation for the complete design rather than for the individual FPGAs in isolation. Additionally, within CR-5000 Board Designer, layout engineers will be able to perform pin swaps that will concurrently update all PCB and FPGA design data, rather than only be able to perform this on request from the FPGA implementation engineer.
Zuken and Aldec are now accepting appointments for product demonstrations and partnership roadmap discussions at DAC 2007, in San Diego, California USA - June 4 - 7. Registrations are currently being accepted: www.aldec.com/services/dac/zuken/
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