IEEE P1581 working group publishes new White Paper

The IEEE P1581 working group is defining a low overhead design-for-test (DFT) methodology to be implemented in memory devices for the support of board- and system-level connectivity test. Additionally, P1581 proposes standard means of access to other (optional) on-chip resources, such as device identification, built-in self test (BIST) and/or built-in self repair (BISR) circuitry.

As a slave to any external test resource (e.g., in-circuit tester (ICT), on-board IEEE Std 1149.1 (JTAG) boundary-scan ICs, board-level BIST circuitry, etc.), P1581 is an alternative for memory devices that might not otherwise implement another formalized DFT infrastructure. Further, a given external master need not be a "test" resource and the P1581-accessible circuitry need not be provisioned solely for "test" purpose.

The P1581 test logic is quite simple and provides for very fast test execution with robust diagnostics. Perhaps more importantly, a P1581 implementation can be achieved without extra (non-mission-mode) device pins.

A white paper; "An Economical Alternative to Boundary Scan in Memory Devices" can be downloaded at http://grouper.ieee.org/groups/1581/documents/P1581_White_Paper_a20070103.pdf .

This white paper provides an overview of various technical details of the proposed standard. The working group would like to solicit comments and opinion of the proposal, aiming to get as much feedback - positive or negative - as possible from the electronics industry, in particular both vendors and users of memory devices.

Please feel free to contact the working group chair (Heiko Ehrenberg, h.ehrenberg@ieee.org) for further information.