Third annual international wafer-level packaging conference set for November 1-3
Mar 20, 2006
The third annual International Wafer-Level Packaging Conference (IWLPC) has been scheduled for November 1-3 at the Wyndham Hotel in San Jose, CA.
The program will consist of one day of workshops followed by two days of specialized presentations and panels by experts in many areas of integrated circuit packaging, including 3D packaging, system-on-package, MEMS and chip-scale packages.
The program will also feature exhibits by leading companies involved in the packaging market.
All paid conference registrants are invited to attend the keynote dinner presentation, scheduled on Thursday night at the Wyndham.
"We are building on and expanding the conference program based on the overwhelmingly positive feedback we received from last year's conference," said Gene Selven, publisher of Chip Scale Review magazine. "We anticipate that attendees at last year's conference, as well as new registrants, will be very pleased with the changes."
The IWLPC is jointly presented by Chip Scale Review and the SMTA. More information is available at smta.org/iwlpc.