JTAG/Boundary Scan test solutions from GĂ–PEL presented at ITC 2005
Nov 02, 2005
At this year's International Test Conference (ITC) in Austin, TX, from November 8 to 10, GĂ–PEL electronic will present its innovative JTAG/Boundary Scan test solutions. The company, which started shipping test systems based on its revolutionary hardware architecture SCANFLEX earlier this year, will use the conference to introduce the first SCANFLEX support for analog JTAG/Boundary Scan compliant to IEEE-Std. 1149.4. Presenting a number of innovative products, GĂ–PEL electronic will position itself as the leading supplier of intelligent solutions for extended JTAG/Boundary Scan at booth number 1606/1608. "We are offering both a unique Integrated Development Environment for JTAG/Boundary Scan applications and a revolutionary hardware solution for unrivalled modularity, flexibility and performance. This extraordinary combination substantially shortens the development cycle of complex JTAG test and programming projects and, at the same time, continuously optimises the fault coverage of various Boundary Scan test processes in interaction with other test strategies," says Heiko Ehrenberg, Manager of US operations for GOEPEL Electronics in Austin, TX. "Together with our partners, we provide extensive experience and know-how in integrating the JTAG/Boundary Scan technology with various ATE strategies such as In-Circuit Test, Flying Probe Test or Functional Test." More information about the company and its product portfolio can be found online at http://www.goepel.com/content/html_en/index.php?site=scan&level1=scan.
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